Standard Delay Format (“SDF”) is a file format used in certain electronic design automation tools to represent timing data of an integrated circuit design. The timing data includes delay information between input and output pins (“arc delays”). Static timing analysis tools generate SDF files for integrated circuit designs SDF files, along with specific test patterns, are then provided as input stimulus to gate level simulators.
The gate level simulators are used to perform simulations of integrated circuit designs. A full chip SDF file provided by a static timing analysis tool contains delays for all timing arcs of the integrated circuit design. These simulations are a critical step in integrated circuit design validation to ensure that a design adheres to its corresponding specification and that there are no violations in the design.
Integrated circuit designs are becoming more and more complex. As transistor sizes continue to shrink, engineers are able to add more logic to integrated circuit designs. With increasingly complex integrated circuit designs, resulting SDF files used in gate level simulation are also increasing in size. Larger SDF files place a burden on gate level simulators by requiring longer runtimes and larger memories. Thus, there is a need to reduce the runtime and memory requirements required of gate level simulators.